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IPC - IPC Standard - IPC J-STD-003C
IPC J-STD-003:
Solderability Tests for Printed Boards
File Format PDF  
Price $35  
Rev c  
Language English    
Number of page    
Date of Publication 2014  
     
         
       

  

J-STD-003 “Solderability Tests for Printed Boards” is the defining standard prescribing test methods, defect definitions and illustrations for assessing the solderability of printed board surface conductors, attachment lands, and plated-through holes utilizing either tin/lead or lead-free solders.

If you are responsible in any way to assure that the printed circuit boards being utilized in your electronic assemblies meet the necessary demands for the soldering process, or that the PCBs being fabricated by your firm meet strict solderability criteria, then this is the program for you.

The objective of this program is to provide an in depth understanding of the solderability test methods described in this standard and to determine the ability of printed board surface conductors, attachment lands, and plated-through holes to wet easily with solder and to withstand the rigors of the printed board assembly processes.

Several test methods are described by which both the surface conductors (and attachment lands) and plated-through holes may be evaluated for solderability. Test A, Test B, Test C, Test D and Test E for tin/lead solder processes and Test A1, Test B1, Test C1, Test D1 and Test E1 for lead-free solder processes, unless otherwise agreed upon between vendor and user. In most instances, Test A and Test C for tin/lead solder processes, Test A1 and Test C1 for lead-free solder processes are used as default solderability tests.


 
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